Gate On Array (GOA) technology is a process technology in which a gate-driving circuit is integrated in the array substrate to replace an external driver chip. GOA technology has features such as reducing production costs and reducing production processes and, thus has a broad application. The gate driving circuit includes a plurality of cascaded shift registers. Each shift register corresponds to a gate line. In the display period of one image frame, the gate driving circuit sequentially provides a scanning signal to each gate line.
FIG. 1 illustrates a schematic view of a shift register in the existing technology. As shown in FIG. 1, the shift register includes four thin film transistors, i.e., a first transistor M11, a second transistor M12, a third transistor M13, and a fourth transistor M14, a capacitor C, a clock signal terminal CLK, an input terminal IN, an output terminal, a reset terminal RESET, an inactive signal terminal VSS, and a pull-up node. In a charging phase of the shift register, the input terminal IN inputs a high level signal, the clock signal terminal CLK inputs a low level signal. And, the first transistor M11 is turned on to charge the capacitor C, and an electric potential of the pull-up node PU is increased. The third transistor M13 is turned on, and the signal output terminal OUT of the shift register outputs the low level signal. In an output phase, the input terminal IN inputs the low level signal, and the clock signal terminal inputs the high level signal. And, the third transistor M13 is turned on, the signal output terminal OUT outputs the high level signal. In addition, under the bootstrapping effect of the capacitor C, the electric potential of the pull-up node is further increased. In a reset phase, the reset terminal RESET inputs the high level signal, the second transistor M12 and the fourth transistor M14 are turned on, such that the pull-up node PU and the signal output terminal OUT are electrically connected to the inactive signal terminal VSS.
In the above process, the pull-up node PU reaches a higher electric potential due to the bootstrapping effect of the capacitor C during the output phase. As a result, the third transistor M13 is subject to a higher bias voltage at the gate electrode, causing the threshold voltage (Vth) characteristics of the third transistor M13 to gradually drift. When the drift reaches a certain degree, switching characteristics of the third transistor M13 will change, resulting in an abnormal signal output, and further a poor display performance.